Memory devices are well known in the electronic field to store and allow accessing to digital information.
Dynamic Random Access Memory (DRAM) is a volatile memory wherein each bit of data is stored in a capacitor and the two possible states of the capacitor, charged or discharged, are conventionally assigned the two logic values of a bit “0” or “1”. Since the electric charge on the capacitors may slowly leak off, DRAM requires an associated refresh circuit which periodically rewrites the data in the capacitors.
One of the largest applications for DRAMs is the use in graphic cards and video game consoles as graphic memories or in portable or stationary devices as main memory.
DRAMs include memory cells of great structural simplicity with only one transistor and a capacitor per cell and for this reason may reach a very high density; however, it requires also a more complex circuitry and timing if compared to other memory devices.
In particular, the write access time is one of the most relevant limitation for the speed and performances of these memory devices since it depends from a complex series of actions that must be completed before a data can be written into a memory cell.
The write access time is given by the combination of more than one timing parameter and one of them of main importance is the minimum column-to-column command timing (known as tCCD or column-to-column delay) or, in other words, the minimum time required to complete a column access of the memory matrix. This parameter is generally set as a multiple of the clock cycle tCK, for instance tCCD may be equal to two clock cycles. At a given column-to-column delay, a limitation in the performances of the memory device is the speed of the write access phase to the sense amplifier.